The present invention relates, in general, to a processor having an improved architecture which can economically perform simulation and fault grading of very large scale digital circuits and, more particularly, to a bus evaluator that can economically preform simulation and fault grading of wired OR buses contained in very large scale digital circuits.
During the design of very large digital circuits, such as VLSI circuits comprising upwards of 100,000 transistors, it is crucial to have available relatively quick means for simulating the performance of a current version of the structure. One type of hardware simulator is described in U.S. Pat. No. 4,587,625 entitled "PROCESSOR FOR SIMULATING DIGITAL STRUCTURES" developed by Joseph T. Marino, Jr. and Ronald V. Chandos and assigned to the same assignee, Motorola Inc.
One particular problem encountered in any hardware simulator is that of evaluating the bus lines. This is normally performed in one of two basic methods. One method consists of defining the bus as a multiple element structure with pyramidally cascaded models, or primitives. This results in unnecessary processing of the additional primitives; increases the size of the simulation database; and creates unrealistic bus timing in the simulation.
Another method is to simulate a bus by: stopping the processing when a bus is encountered; reading all of the data necessary to evaluate the bus; and continue processing. Either of these methods would require a great deal of processing time and the processing may have to be halted while the decision is being made.